Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6-T) SRAM, eight-transistor (8-T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into, or reading a bit from, the SRAM cell.
With the increasing down-scaling of integrated circuits, the operation voltages of the integrated circuits are reduced, along with the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which measure how reliably the bits of the SRAM cells can be read from and written into, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.
Various approaches have been explored to lower VCCmin, which is the minimum operation voltage VCC required for reliable read and write operations, and to suit the ever-decreasing operation voltages. For example, a negative bit-line technique was used to improve cell write-ability at low operation voltage, particularly when the word-line voltage is suppressed. Referring to FIG. 1, which is a 6-T SRAM cell, a “0” bit is to be written into the illustrated SRAM cell. Bit-line BL hence carries a low voltage representing a logic low and bit-line BLB carriers a high voltage representing a logic high. Node 10 is at a high voltage, while node 12 is at a low voltage. To write a “0” bit into the SRAM cell, a negative voltage, for example, −100 mV, is put on bit-line BL. The negative voltage causes an increase in the voltage difference between node 10 and bit-line BL. Accordingly, the write operation becomes easier and VCCmin may be reduced.
The negative bit-line technique, however, comes with a price. Typically the negative voltage is generated using a charge pump (not shown), which receives operation voltage VDD and outputs the negative voltage. FIG. 2 schematically illustrates the relationship between operation voltage VDD and the negative bit-line voltage generated by the charge pump. It is noted that if operation voltage VDD becomes lower, the magnitude of the negative voltage also reduces, if the same charge pump is used. This trend, however, defeats the purpose of having the negative bit-line voltage. As is well perceived, if operation voltage VDD is reduced, the magnitude of the negative bit-line voltage needs to be greater in order to offset the reduction in operation voltage VDD. One way to solve this problem is to adopt larger charge pumps when operation voltage VDD is reduced. However, such a solution requires more chip area. Alternative solutions are thus needed.